1. Field of the Invention
The present invention relates to controllable oscillators and in particular to digitally controllable oscillators usable for clock extraction, clock recovery, synchronization, etc., within or outside a phase lodge loop.
2. Description of the Related Art
In data transmission technology there is a general need for extracting a clock from a data stream. A data transmission standard which recently spread increasingly is the USB standard (USB=universal serial bus). The USB standard standardizes a data transmission format for a fast data transmission between USB devices and a host. The USB standard defines a so-called tier-star-topology, wherein USB devices may either be hubs or functions or functional devices, respectively. The USB data format is specified in the USB specification. The most current USB definition is currently USB revision 2.0.
The USB bus is a semi-duplex bus. All transactions are initiated by the host. In the USB specification revision 2.0 three data transmission rates are defined. The lowest data transmission rate is used in the low-speed mode and comprises 1.5 megabits per second. In the full-speed mode a data transmission rate of 12 megabits per second is used.
In the high-speed mode a data transmission rate of 480 megabits per second is used.
The use of the low-speed mode serves for interactive devices, like e.g. a keyboard or a mouse. Only a limited number of low-speed devices should be connected to the bus in order to prevent a degradation of the bus efficiency. For full-speed and high-speed devices a special bandwidth and latency are guaranteed.
Devices are connected to the USB bus via a 4-wire cable, carrying differential data, a power signal and mass. This means, that one core of the 4-wire cables carries a positive differential signal Dp, that a further core of the 4-wire cables carries a negative differential signal Dn and that a further core is on the supply potential and that finally the last core is on the mass potential. The clock information is encoded in the data. According to the USB specification an NRZI encoding and a bit stuffing technology are used in order to guarantee an adequate number of transitions. NRZI means no return to zero invert. This means, that an inverse encoding is used. A logical “1” signal is represented by a non-present change in an electrical signal, while a logical “0” signal is represented by a change of state of the electrical signal. One edge thus represents a zero, while a non-present change, i.e. a steady-state signal, represents a zero. Further, for a steady component reduction a bit stuffing is used, so that after six subsequent ones a positive/negative edge is used.
As it is illustrated in FIG. 7b, the data stream is defined as a series of frames 72, 73, which are separated from each other by so-called control characters 74, wherein the ticks occur at an interval of 1 ms. Within the frame 72 or 73 a plurality of data packets is located. This means that a frame consists of several data packets and that a data stream consists of a plurality of subsequent frames. Each data packet is introduced in the data stream by a packet identification number having a width of 8 bits and illustrated in FIG. 7c. One frame thus includes as many packet identification numbers (PID) as there are packets in the frame. The specification of the packet identification number illustrated in FIG. 7c which is four bits wide and presented in a PID field by the four PID bits PID0, PID1, PID2, PID3 and by the correspondingly inverted PID bits, is determined in the USB standard. The bits represented in FIG. 7c are arranged from the LSb to the MSb. LSb stands for least significant bit, while MSb stands for most significant bit.
The host transmits a start of frame packet (SOF packet) once per millisecond in order to define the ticks 74 represented in FIG. 7b. The SOF packet is represented in FIG. 7d and includes an SYNC field (not illustrated in FIG. 7d), an SOF-PID field 75, an 11-bit frame number (76) and a CRC check sum for the field 76 which is entered into a field 77. The frame number 76 is incremented by 1 with every additional SOF packet.
In FIG. 7a, for example, the synchronization pattern (SYNC pattern) preceding the PID field 75 of FIG. 7d is illustrated as an electric signal. It consists of a sequence of bits specified in the USB standard or of a data pattern, respectively, that looks as illustrated in FIG. 7a as an electric signal due to the NRZI encoding. The sequence of databits is 00000001, which leads to the “electric” sequence 10101011 shown in FIG. 7a. Before the synchronization data pattern an area designated by idle is located comprising with regard to the differential signals Dp and Dm a single-ended zero encoding (SE0 encoding), as it is discussed in the following. This SE0 encoding of the Dp and Dm signals indicates the end of the preceding frame and further indicates that now a new frame follows that is introduced by a synchronization field and is directly followed, as it is shown in FIG. 7a, by the packet identification number and in particular, as it is shown in FIG. 7c, a least significant bit of the PID and the next high-order bit of the PID, etc.
The notation shown in FIG. 7a illustrates that the bits are fixed in the synchronization pattern and that the associated electric signal can have the sequence of 10101011, while the PID bits may have both a 0 or a 1, depending on the packet identification to be encoded.
Every low-speed or full-speed data packet transmitted via the USB bus thus starts with a synchronization pattern (FIG. 7a) followed by the packet identification number (PID), as illustrated in FIG. 7c, which defines the packet type. The synchronization field includes a series of 0–1 transitions on the bus in order to enable a receiver to synchronize onto the bit clock.
As it is illustrated in FIG. 7, a frame interval of one millisecond is defined. The host transmits an SOF packet (start of frame packet) once per millisecond (FIG. 7b). The SOF packet consists of a synchronization field followed by the SOF-PID, an 11-bit frame number and a CRC 5-finger print (FIG. 7d). The frame number is incremented with every SOF packet sent.
When a device is connected to the USB bus, a startup sequence takes place. At the end of this sequence the device is driven into a reset state. After the reset event the device has a time period of 10 milliseconds in order to perform a reset recovery. During this time the device receives SOF packets.
A conventional USB device is schematically illustrated in FIG. 9. It includes an analog USB front end that may be integrated with a differential transmitter (TX) and a differential receiver (RX) in a functional unit 90. At one side of the element 90 the signals Dp and Dm are present in analog form, while at another side of the element 90 the corresponding received and analog/digital-converted signals are applied that are fed into a USB core 91 or are received from the same, respectively. These signals are illustrated in FIG. 9 by the two pairs of parallel signal arrows. The USB device further includes a crystal oscillator 92 connected to a crystal oscillator wiring 93, wherein the crystal oscillator wiring 93 on the one hand controls the USB core 91 and on the other hand a clock distribution 94 connected to a CPU 95 which is again in operational connection with a memory 96. Further, a USB device, depending on the application, also includes a parallel input/output interface (parallel I/O) 97.
Such conventional USB devices typically use a crystal oscillator 92 as a clock source for the system devices and the USB data recovery circuit, as it may be seen from FIG. 9. For robust portable devices, like e.g. chip cards, it would be desirable that they extract their own local clock directly from the USB data stream. For such devices the use of crystal oscillators is impractical, as crystals may usually not be integrated into a chip and are further very prone to damage due to mechanical loads. Chip cards are usually carried in rough environments, like e.g. in a purse carried in a trouser pocket. The thus exerted mechanical load would be fatal for a quartz crystal oscillator.
For synchronization applications in general, however also for other purposes, digitally controllable oscillators are required. Such digitally controllable oscillators normally include a controllable oscillator that generates an oscillation with a certain frequency depending on an analog input signal. If the analog input signal is increased or decreased, then typically also the frequency becomes higher or lower. In order to achieve a digital controllability the analog input of the controllable oscillators is connected to a digital/analog converter. By inputting a digital value into the digital/analog converter a certain analog output signal is generated which depends on the digital input signal.
What is disadvantageous about such a digitally controllable oscillator is that the digital/analog converter is always restricted to a certain bit width associated with a signal swing of the analog output signal which finally determines the controllability of the controllable oscillator. Controllable oscillators typically have a bottom frequency which is for example achieved when only zeros are input as a binary word in the digital/analog converter. The highest frequency of the controllable oscillator is achieved when as a binary word only ones are input into the digital/analog converter. The binary weighting that digital/analog converters generally have, and the requirement that a digital/analog converter must generate a maximum output signal and a minimum output signal that are adjusted to the control area of the oscillator, which consequently have to be selected so that the on the one hand the minimum frequency of the controllable oscillator and on the other hand the maximum frequency of the controllable oscillator are obtained, automatically results in a consequence with regard to the quantization of the frequency or the granularity of the frequency setting, respectively.
The quantization of the frequency setting is determined, i.e. the minimum increment by which the analog output signal of the digital/analog converter which is simultaneously the analog input signal in the controllable oscillator, and thus the frequency of the oscillator may be varied.
If the binary input word in the digital/analog converter is increased by a digital increment, then at the output of the digital/analog converter a difference in the analog output signal results which causes the frequency of the controllable oscillator to rise by a certain amount. As an example, the following situation results. If a binary input word of for example 1000 is increased in the digital/analog converter by a digital increment, i.e. by a change of the least significant bit (LSB), i.e. if instead of 1000 the binary value of 1001 is entered, then the analog output signal is higher by a certain differential value as, which leads to the fact that the frequency of the controllable oscillator again rises or falls by a certain frequency differential value σs.
This quantization may in some cases be too coarse, in particular when synchronization circuits are considered in which very slight frequency changes are required, as a very accurate synchronization is desired.
DE 10041772 C2 discloses a clock generator in particular for USB devices in which due to a synchronization signal periodically recurring in the data stream a pulse filter is controlled in order to reduce the frequency of a pulse train output by an internal clock generator by suppressing pulses in the effective frequency. Further, using the synchronization signal and a value stored in a pulse number storage or using an output signal of a data signal decoder, respectively, a frequency generated by the internal clock generator is re-tuned.
In order to increase this differential value, either the width of the digital/analog converter could be increased such that the same obtains a larger area of representable numbers. This is not desirable in some applications, however, as digital/analog converters in particular in integrated circuits are predetermined with regard to layout/design. On the other hand, the digital/analog converter could be reduced with regard to its supply or reference voltage, respectively, such that the maximum binary word leads to a lower maximum output signal and thus of course also to a lower as for a digital frequency increment. This option has the disadvantage, however, that then the maximum control range of the controllable oscillator may not be used any more, which is in particular disadvantageous when applications are present in which large frequency changes are caused by the system. Such scenes for example occur in frequency-hopping applications.